It has been a recent trend in dynamic random access memory (DRAM) to increase the density of DRAM circuits. However, as higher density DRAM cells are developed, the area available for capacitors that are used in the DRAM cells decreases. In order to decrease the area of capacitors while maintaining reliability standards, it is important to be able to maintain the capacitance of each capacitor while decreasing its footprint. Recently, capacitors having a three dimensional structure have been suggested to increase cell capacitance. Such capacitors include, for example, double stacked, fin structured, cylindrical, spread stacked, and box structured capacitors.
One of the most popular methods for increasing the capacitance of a DRAM capacitor is the use of hemispherical grain (HSG) polysilicon. The deposition of HSG polysilicon allows an increase in the surface area of the storage nodes of the capacitor. Typically, HSG polysilicon is formed using a seeding and high vacuum technique. In summary, silane or di-silane is used to seed the surface of the underlying silicon. Next, the HSG polysilicon is formed in a high vacuum. It should be noted that the formation of HSG silicon is a well known technique as exemplified by U.S. Pat. No. 5,837,580 to Thakur et al. See also U.S. Pat. No. 5,639,685 to Zahurak et al.
However, it has been found that when the HSG polysilicon is formed, a thin, undoped silicon layer will be formed on the surface of the HSG. This results in a capacitance depletion effect on the order of 15%. To overcome the effect, a highly doped electrode layer of amorphous silicon must be used in the process. The use of this doped electrode layer will tend to inhibit silicon migration and cause poor HSG growth. Thus, the use of the highly doped amorphous silicon layer is not favorable for HSG formation.
It has also been proposed that a PH.sub.3 treatment at 750 degrees Celsius or ion implantation be used to increase the dopant level on the grain surface after the formation of the HSG.
What is needed is a method for reducing the capacitance depletion effect during the synthesis of HSG silicon.